The present invention relates to a register designating system and an in-register data alignment processing in an SIMD (Single Instruction Multiple Data) processor, and relates to means for executing in-register data alignment without deteriorating a parallel processing function of SIMD at high speed.
Further, the present invention relates to means for operating standard multiply accumulate operation as a DSP (Digital Signal Processing) instruction while maintaining parallelism of SIMD without deteriorating accuracy.
Japanese Patent Laid-Open No. 124484 has disclosed a method of executing vector operation such that a plurality of consecutive registers can be designated by a single register designating field, when a vector operation processing, which is necessary in three-dimensional graphics or the like, is executed.
Further, as an in-resister data alignment instruction, various data alignment instructions, which can designate up to four operands, are described in “AltiVec Programming Interface Manual” of an instruction set Altivec for multimedia developed by Motorola Corporation.
Further, with regard to multiply accumulate operations, a multiply accumulate instruction, without deteriorating accuracy, is realized in the form of halving reduced parallelism of SIMD from 4 parallel to 2 parallel by an SH5 architecture developed jointly by Hitachi, Ltd. and ST Microelectronics.
According to the vector operation processing disclosed in Japanese Patent Laid-Open No. 124484, a constitution capable of designating only a multiple of 4 registers and therefore, which is devoid of freedom. Further, according to the data alignment instruction of Altivec, not only an operating apparatus is large-sized and expensive, but also only three source registers can be designated, and operation particular to SIMD such as data pack or unpack cannot be executed efficiently. Therefore, the parallelism of SIMD cannot fully be achieved.